School of CHIPS (CHIPS), Xi’an Jiaotong-Liverpool University (XJTLU), is launching AY 2026-2027 Syntegrative Projects (SE) in microelectronics and integrated circuits. SE adopts a “technology + entrepreneurship” project-driven model, embedding real industrial needs into the curriculum under a dual-mentorship system (on-campus CHIPS supervisor + enterprise supervisor). All projects cover the full chain from design and fabrication to testing, system integration, and technology transfer, aiming to cultivate students’ engineering capabilities, interdisciplinary collaboration, and industrial vision. Completed projects count toward PDP certification and participation in the annual showcase.
Milestones：
2026/10/12-2027/10/31
Student application release
2026/11/01-2027/05/31
Project implementation
2027/06/01-2027/06/15
Showcase and expert evaluation
Note: Each project normally admits no fewer than 2 and no more than 6 students.
Responsibility division
All SE projects adopt a dual-supervisor mechanism. Both supervisors participate jointly in the project kick-off, mid-term review, and final evaluation. The on-campus supervisor must be from the School of CHIPS and is responsible for defining the main technical route, ensuring academic integrity, and managing intellectual property ownership. The enterprise supervisor serves as a consultant or co-supervisor, monitors progress quarterly, and provides guidance on engineering practice and commercialization.
Available Projects
(1) A study on the MicroLED-Based Interconnect System for High-Efficiency Datacenter Communication
Led by the School of CHIPS, the on-campus supervisor is Dr. Qifeng Lu.
Description: Design and fabrication of an optical interconnection system based on MicroLED, including TX/RX PCB, transimpedance amplifier, microlens coupling, FPGA physical layer, Hamming error correction, and bit-error-rate (BER) testing.
Expected outcomes: Hardware prototype, BER test report, demonstration video/poster.
(3) AI-Enhanced RF Sensing for Smart Health: Design, Optimization, and Fabrication of Harmonic Tags
Led by the School of CHIPS, the on-campus supervisor is Dr. Arjun Kumar.
Description: Equivalent-circuit modeling of passive harmonic tags (including parasitic elements and varactors), AI-driven automatic optimization of the antenna and matching network, and anechoic-chamber measurements from −30 to +3 dBm.
Expected outcomes: Three functional tags, MATLAB or open-source optimization framework, measurement dataset, journal paper, patent.
(4) Semi-Automated Image Analysis of Colloidal Gold Lateral Flow Test Strips
Led by the School of CHIPS, the on-campus supervisor is Dr. Qi Li.
Description: Python-based processing of smartphone-captured images; semi-automatic localization of test and control lines, background subtraction, T/C ratio calculation, and baseline comparison with ImageJ.
(5) Image processing system based on Ehiway Microelectronic FPGA
Led by the enterprise partner, Ehiway Microelectronic Science and Technology (Suzhou) Co. Ltd.
Description: Implementation of a basic image processing system on Ehiway FPGA, covering image acquisition, processing, and display. The acquisition part requires real-time capture; the processing part requires hardware acceleration of algorithms for object recognition and detection (using traditional methods such as shape, color, or texture feature extraction, followed by classifier design).
AY 2026-2027 Syntegrative Projects Launch
School of CHIPS (CHIPS), Xi’an Jiaotong-Liverpool University (XJTLU), is launching AY 2026-2027 Syntegrative Projects (SE) in microelectronics and integrated circuits. SE adopts a “technology + entrepreneurship” project-driven model, embedding real industrial needs into the curriculum under a dual-mentorship system (on-campus CHIPS supervisor + enterprise supervisor). All projects cover the full chain from design and fabrication to testing, system integration, and technology transfer, aiming to cultivate students’ engineering capabilities, interdisciplinary collaboration, and industrial vision. Completed projects count toward PDP certification and participation in the annual showcase.
Note: Each project normally admits no fewer than 2 and no more than 6 students.
All SE projects adopt a dual-supervisor mechanism. Both supervisors participate jointly in the project kick-off, mid-term review, and final evaluation. The on-campus supervisor must be from the School of CHIPS and is responsible for defining the main technical route, ensuring academic integrity, and managing intellectual property ownership. The enterprise supervisor serves as a consultant or co-supervisor, monitors progress quarterly, and provides guidance on engineering practice and commercialization.
(1) A study on the MicroLED-Based Interconnect System for High-Efficiency Datacenter Communication
Led by the School of CHIPS, the on-campus supervisor is Dr. Qifeng Lu.
Description: Design and fabrication of an optical interconnection system based on MicroLED, including TX/RX PCB, transimpedance amplifier, microlens coupling, FPGA physical layer, Hamming error correction, and bit-error-rate (BER) testing.
Expected outcomes: Hardware prototype, BER test report, demonstration video/poster.
Enterprise partner: Suzhou SkiteLight Optoelectronics Technology Co., Ltd.
Supervisor email: Qifeng.Lu@xjtlu.edu.cn
(2) Processing and On-wafer Characterization of Metal-Oxide based Sensors for Next-Generation Greenhouse Gas Detection
Led by the School of CHIPS, the on-campus supervisor is Dr. Jang Yong Kim.
Description: RF magnetron sputtering and annealing of Sn-doped In₂O₃ thin films, combined with photolithography, interdigitated electrodes, and MEMS processes; low-temperature NO₂/SO₂ detection and wafer-level characterization (SEM, XRD, XPS, AFM, probe station).
Expected outcomes: Sensor prototype, material and gas-sensing dataset, journal paper, conference presentation.
Enterprise partner: MicroElab Technology Co., Ltd. (Suzhou)
Supervisor email: JangYong.Kim@xjtlu.edu.cn
(3) AI-Enhanced RF Sensing for Smart Health: Design, Optimization, and Fabrication of Harmonic Tags
Led by the School of CHIPS, the on-campus supervisor is Dr. Arjun Kumar.
Description: Equivalent-circuit modeling of passive harmonic tags (including parasitic elements and varactors), AI-driven automatic optimization of the antenna and matching network, and anechoic-chamber measurements from −30 to +3 dBm.
Expected outcomes: Three functional tags, MATLAB or open-source optimization framework, measurement dataset, journal paper, patent.
Enterprise partner: Suzhou Qiuxiu Technology Co., Ltd.
Supervisor email: Arjun.Kumar@xjtlu.edu.cn
(4) Semi-Automated Image Analysis of Colloidal Gold Lateral Flow Test Strips
Led by the School of CHIPS, the on-campus supervisor is Dr. Qi Li.
Description: Python-based processing of smartphone-captured images; semi-automatic localization of test and control lines, background subtraction, T/C ratio calculation, and baseline comparison with ImageJ.
Expected outcomes: Executable scripts, comparison report, technical documentation, exhibition poster.
Enterprise partner: Jiangsu Asyla Biotechnology Co., Ltd.
Supervisor email: Qi.Li02@xjtlu.edu.cn
(5) Image processing system based on Ehiway Microelectronic FPGA
Led by the enterprise partner, Ehiway Microelectronic Science and Technology (Suzhou) Co. Ltd.
Description: Implementation of a basic image processing system on Ehiway FPGA, covering image acquisition, processing, and display. The acquisition part requires real-time capture; the processing part requires hardware acceleration of algorithms for object recognition and detection (using traditional methods such as shape, color, or texture feature extraction, followed by classifier design).
Expected outcomes: Executable scripts, technical report, exhibition poster.
On-campus supervisor: Dr. Zongjie Shen
Supervisor email: Zongjie.Shen02@xjtlu.edu.cn
All projects are managed by the School of CHIPS and its SE Program Committee. Contact details are as follows,